The present disclosure relates to semiconductor devices and methods for fabricating the same, and specifically to a field-effect semiconductor device using a nitride semiconductor and a method for fabricating the same.
In recent years, field-effect transistors (FETs) using a gallium nitride (GaN)-based semiconductor material have been actively researched as power devices.
Since a nitride semiconductor material such as GaN can form various alloy crystals with aluminum nitride (AlN), indium nitride (InN), etc., the nitride semiconductor material can form a hetero junction similar to a conventional arsenic-based semiconductor material such as gallium arsenide (GaAs). In particular, a hetero junction of a nitride semiconductor has the feature that even when the nitride semiconductor is undoped, highly-concentrated carriers are generated at a hetero junction interface due to spontaneous polarization or piezo-polarization. As a result, when a FET is made of nitride semiconductor, the FET is more likely to be depletion type (normally-on type), and thus it is difficult to obtain enhancement type (normally-off type) characteristics. However, most devices currently available in power electronics markets are normally-off type, and there is thus a strong need also for normally-off type GaN-based nitride semiconductor devices.
Normally off-type transistors have, for example, a configuration in which the threshold voltage of a gate is shifted to have a positive value by burying a gate formation region (see, for example, T. Kawasaki et al., Solid State Devices and Materials 2005 tech. digest p. 206), or are fabricated by, for example, a method that includes forming a FET on the (10-12) plane, which is a plane orientation of a crystal plane in a substrate made of sapphire, to prevent generation of a polarization electric field in a direction of crystal growth of the nitride semiconductor (see, for example, M. Kuroda et al., Solid State Devices and Materials 2005 tech. digest p. 470). Here, for the sake of convenience, a minus sign “−” attached to each miller index of the plane orientation indicates inversion of an index following the minus sign.
Moreover, as a promising structure for achieving a normally-off FET, a junction field-effect transistor (JFET) including a p-type GaN layer formed in a gate formation region has been proposed (see, for example, Japanese Unexamined Patent Publication No. 2005-244072).
In the JFET, piezo-polarization occurring at a first hetero junction between a channel layer made of undoped GaN and a barrier layer made of undoped AlGaN is canceled by another piezo-polarization occurring at a second hetero junction between a barrier layer made of AlGaN and a p-type GaN layer on the bather layer made of AlGaN. This can selectively reduce the two-dimensional electron gas concentration directly under the gate formation region where the p-type GaN layer is formed, so that the JFET can have normally-off characteristics. Moreover, by using for a gate electrode, a pn junction having a higher built-in potential than a Schottky junction between metal and a semiconductor, a rising voltage of the gate can be increased. This provides advantages that a gate leakage current can be reduced even when a positive gate voltage is applied.
FIG. 12 illustrates a cross-sectional structure of a JFET as a first conventional example, where a p-type GaN layer is provided in a gate formation region.
As illustrated in FIG. 12, a buffer layer 2 made of aluminum nitride (AlN), a channel layer 3 made of undoped gallium nitride (GaN), a bather layer 4 made of undoped aluminum gallium nitride (AlGaN), and a p-type GaN layer 5 are sequentially formed on a substrate 1 made of, for example, silicon (Si). Note that the undoped nitride semiconductor means a nitride semiconductor into which impurities determining the conductivity type are not implanted on purpose.
A gate electrode 7 made of palladium (Pd) is selectively formed on the p-type GaN layer 5. Here, the p-type GaN layer 5 has been removed except a portion of the p-type GaN layer 5 under and on both sides of the gate electrode 7. A source electrode 8 and a drain electrode 9 which are made of Ti/Al are formed on the barrier layer 4, the source electrode 8 and the drain electrode 9 being spaced apart from the p-type GaN layer 5.
FIGS. 13A-13E illustrates a method for fabricating the JFET according to the first conventional example.
First, as illustrated in FIG. 13A, a buffer layer 2 made of AlN, a channel layer 3 made of undoped GaN, a bather layer 4 made of undoped AlGaN, and a p-type GaN layer 5 are sequentially formed on a substrate 1 by molecular beam epitaxy or metal organic chemical vapor deposition.
Next, as illustrated in FIG. 13B, a resist film 10 patterned to have a predetermined size as a gate formation region is formed on the p-type GaN layer 5.
Then, as illustrated in FIG. 13C, using the patterned resist film 10 as a mask, dry etching is performed on the p-type GaN layer 5 to remove the p-type GaN layer 5 except a portion of the p-type GaN layer 5 in a gate formation region.
Then, a resist film (not shown) which has an opening pattern exposing formation regions for a source electrode and a drain electrode is formed on the p-type GaN layer 5, and a Ti layer and an Al layer are stacked on the resist film. Thereafter, unnecessary portions of the stacked metal layers are removed together with the resist film by a lift-off method, thereby obtaining a source electrode 8 and a drain electrode 9 as illustrated in FIG. 13D. After that, the Ti/Al layer is alloyed in an infrared ray alloying furnace or a heater alloying furnace.
Next, a resist film (not shown) which has a gate pattern as an opening pattern is formed on the p-type GaN layer 5. Then, a Pd layer is formed on the resist film having the gate pattern. Subsequently, an unnecessary portion of the Pd layer is removed together with the resist film by a lift-off method, thereby completing a JFET as illustrated in FIG. 13E.
In the first conventional example, if it is possible to form the gate electrode 7 and the source electrode 8 or the drain electrode 9 close to each other, that is, if the device size can be reduced, the channel length is reduced, so that the channel resistance (source resistance) decreases. Therefore, it is also possible to increase transconductance. Additionally, the reduction in device size can increase the number of devices obtained per area.
Incidentally, in the method for fabricating the JFET according to the first conventional example as illustrated in FIG. 13D, the width of the p-type GaN layer 5 in a gate length direction has to be sufficiently large compared to the width of the gate electrode 7 in the gate length direction. The term “sufficiently large” means a size allowing formation of the gate electrode 7 with high precision while preventing the gate electrode 7 from slipping down from an upper surface of the p-type GaN layer 5. When the gate electrode 7 slips down from the p-type GaN layer 5, the gate leakage current is significantly increased. Specifically, the width of the p-type GaN layer 5 in the gate length depends on the mask alignment accuracy in a stepper device. When a general i-line stepper device is used, the width of the p-type GaN layer 5 is preferably greater than the width of the gate electrode 7 by about 1 μm.
Moreover, it is not preferable that the p-type GaN layer 5 come into contact with the source electrode 8 or the drain electrode 9 because also in this case, the gate leakage current increases.
Thus, in the fabrication method according to the first conventional example, the p-type GaN layer 5 requires a further width in addition to the width of the gate electrode 7. For this reason, the source electrode 8 and the drain electrode 9 are necessarily formed with a required distance from side surfaces of the p-type GaN layer 5. That is, the distance between the gate electrode 7 and the source electrode 8 or the drain electrode 9 is extra long, which is a problem in terms of reduction in size of the semiconductor device.
As an example solution of the above-described problem related to the reduction in size includes a method for dry-etching the p-type GaN layer by using the gate electrode as a mask in a self-alignment manner (see, for example, Japanese Unexamined Patent Publication No. S62-281476).
FIG. 14 illustrates a cross-sectional configuration of a JFET formed in self-alignment manner as a second conventional example. As illustrated in FIG. 14, n+-type source/drain regions 12 are formed on the semiconductor substrate 11 with an n-type channel region 13 provided between the n+-type source/drain regions 12. A p+-type gate region 14 and a gate electrode 15 on the p+-type gate region 14 are sequentially formed between the source/drain regions 12 and on the channel region 13. Moreover, a source electrode 16 is formed on one of the source/drain regions 12, and a drain electrode 17 is formed on the other of the source/drain regions 12.
As described above, with self alignment, the width of the gate electrode 15 and the width of the gate region 14 which is the p+-type conductive layer can be equal to each other in the gate length direction, so that the size of the semiconductor device can be reduced.